Fig. 5: Reliability and performance benchmark of the steep-slope TS-VTFET.
From: Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures
a DC pulse stressing test of the TS-VTFET. b DC stressing of the TS-VTFET under the threshold voltage of the TS cell. c Comparison of SS and Ion/Ioff ratio at room temperature between the demonstrated TS-VTFET and previously reported VTFETs, including the organic semiconductor (OSC)-based vertical organic FET (VOFET)13, Si VTFET9, graphene/MoS2 VTFET38, IGZO/graphene VTFET14, VTFET with MXene Ti3C2Tx/Organic semiconductor PDVT-1020, MoS2/graphene VTFET39, WS2/graphene vertical tunnelling transistors16, black phosphorous (BP)/MoS2 VTFET29, MoS2/MoTe2 VTFET40 and MoS2/graphene VTFET15. Here, the Ion/Ioff refers to the drain current modulation ratio between the maximum (ON) and minimum (OFF) current level during gate voltage sweeping. Device parameters of the TS-VTFET are taken from the transfer characteristics measured at Vd = 0.3 V.
