Fig. 4: Charge Shuttling.
From: Spin-EPR-pair separation by conveyor-mode single electron shuttling in Si/SiGe
a Charge scan of the DQD under gates P1 and S1 with labelled electron filling. Voltage pulse (red triangle → S → T) of the initialisation in (3,1) is marked (Stage T is at B2 = 0.7 V). Inset: Schematic of the electrostatic potential along the 1DEC under gates B1, P1 and B2 for loading. The respective electrostatic configurations are marked with red and blue triangles. b Shuttle Pulse. Schematic of the electrostatic potential under the labelled gates after initialisation (top). Sinusoidal voltage pulse VSi(τS) applied to S1 − S4 to shuttle the electron one period (λ = 280 nm) forward (bottom). c Flowchart of the charge shuttling experiment. Labelled points correspond to panels a and b and Fig. 1b. Coloured arrows in the load and shuttle sections express that during this part of the pulse other gates than P1 and B2 are pulsed. The pulse stages M and red triangle are electrostatically the same. d Charge shuttling fidelity as a function of shuttle pulse amplitude Ulower at f = 10 MHz. e Charge shuttle fidelity as a function of the shuttle pulse frequency f at Ulower = 150 mV. Inset: Histogram of SET-currents measured during point M with assigned filling numbers of the QD underneath gate P1.
