Table 1 List of reported prototypes in the literature and the detail of how was implemented each block (Software/Hardware Off-chip/Hardware On-chip, etc)
From: Hardware implementation of memristor-based artificial neural networks
Work(s) | Device | NN Type/ Dataset | Crossbar size | CMOS Node | ADC | Cell Structure | Input circuit (DAC) | Sensing Electronics | Activation function | Row/Col. Selectors | Softmax Activation Func. | Inference/training | Weight Prog. circuitry |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Au/Pd/WOX/Au | SLP, Sparse coding, MLP/Greek letters | 54 × 108 | 180 nm | On-chip (13-bit) | 1R | On-chip (6-bit) | Charge integration | On-chip digital (Sigmoid) | On-chip | Off-chip (Software) | Inference & training | On-chip | |
TiN/TaOx/HfOx /TiN | CNN/MNIST | 128 × 16 | 130 nm | Off-chip (8-bit) | 1T1R | On-chip (1-bit) | Charge integration | Off-chip (software: ReLU and max. Pooling) | On-chip | Off-chip (Software) | Inference & training | Off-chip | |
Pt/Ta/Ta2O5/Pt/Ti | MLP/MNIST | 128 × 64 | 2 µm | N/A | 1T1R | N/A | N/A | Off-chip hardware: ReLU) | Off-chip | Off-chip (Software) | Learning & training | Off-chip | |
No data (propietary dev.) | BNN, MNIST, CIFAR-10 | 128 × 64 | 90 nm | On-chip (3-bit) | 1T1R | Not implemented | On-chip (VSA) | On-chip (Binary) | On-chip | Off-chip (software)* | Inference only | Off-chip | |
Ta/TaOx/Pt | CNN/MNIST | 64 × 64 | 180 nm | On-chip | 1T1R | On-chip | On-chip (TIA) | Off-chip (software)* | On-chip | Off-chip (software)* | Inference only | Off-chip | |
TaOx | CNN/MNIST | 64 × 64 | 180 nm | On-chip (10-bit) | 1T1R | On-chip | On-chip (TIA) | Off-chip (software)* | On-chip | Off-chip (software)* | Inference only | Off-chip | |
219, | W/TiN/TiON | BNN/MNIST | 100 × 100 | 65 nm | On-chip (3-bit) | 1T1R | N/A | On-chip (CSA) | Off-chip (FPGA: max. Pooling) | On-chip | Off-chip (FPGA) | Inference only | Off-chip |
Pt/SiOxAg/Pt/Ti, Ta/Pd/HfO2/Pt/Ti | CNN/ ‘U’, ‘M, ‘A’, ‘S’ | 8 × 8 | No data | Off-chip | 1T1R | On-chip | Off-chip (TIA) | On-chip (ReLU), Off-chip (software: max. Pooling) | Off-chip | Off-chip (MCU) | Inference & training | Off-chip | |
TiN/HfO2/Ti/TiN | BNN/MNIST, CIFAR-10 | 1 Kb | 130 nm | On-chip | 2T2R | Not implemented | On-chip (PCSA) | On-chip (Binary) | On-chip | On-chip (Binary) | Inference only | Off-chip | |
W/Ta2O5/TaOx/W | MLP/MNIST | 2 Mb | 180 nm | On-chip (1-bit) | 1T1R | On-chip (1-bit) | On-chip | No data | On-chip | No data | Inference only | Off-chip | |
AlCu/TiN/Ti/HfO2/TiN | MLP/ | 32 × 32 | 150 nm | On-chip (1 or 3-bit) | 1T1R | On-chip (1-bit) | On-chip | Off-chip (software)* | On-chip | Off-chip (software)* | Inference only | On-chip (SRAM) | |
PCM (no more data) | MLP/MNIST | 512 × 1024 | 180 nm | No data | 3T1C+ 2PCM | No data | Off-chip (software) | Off-chip (Software: ReLU) | Off-chip | Off-chip (Software) | Inference only | Off-chip | |
PCM (no more data) | MLP/MNIST, ResNET-9/CIFAR-10 | 256 × 256 | 14 nm | On-chip | 4T4R | On-chip (8-bit) | On-chip (CCO-based) | On-chip (ReLU) | On-chip | Off-chip (Software) | Inference only | On-chip | |
72, | PCM (no more data) | MLP/MNIST | 512 × 512 | 14 nm | Off-chip | 4T4R | On-chip (8-bit) | On-chip | Off-chip (Sigmoid) | On-chip | Off-chip (FPGA) | Inference only | On-chip |
No data | CNN/ CIFAR-10 | 256 × 512 | 55 nm | On-chip | 1T1R | No data | On-chip | Off-chip (FPGA) | On-chip | Off-chip (FPGA) | Inference only | Off-chip | |
TiN/HfO2/Ti/TiN | CNN/MNIST | 18 kB | 130 nm | Off-chip* | 1T1R | Off-chip* | Off-chip* | Off-chip (FPGA) | Off-chip* | Off-chip (FPGA) | Inference only | On-chip | |
TiN/HfO2/Ti/TiN | BNN/MNIST | 1 Kb | 130 nm | N/A | 2T2R | N/A | On-chip | Off-chip (software)* | On-chip | Off-chip (software)* | Inference only | Off-chip | |
-/HfO2/TaOX/- | MLP/MNIST | 158.8 Kb | 130 nm | On-chip (8-bit) | 2T2R | On-chip (8-bit) | Charge integration | Off-chip | On-chip | Off-chip | Inference only | Off-chip (FPGA) | |
TiN/HfO2/TaOX/TiN | CNN/MNIST, CIFAR-10 | 256×256 | 130 nm | On-chip (8-bit) | 1T1R | On-chip | Charge integration | On-chip (analog: ReLU), Off-chip (FPGA: max. Pooling) | On-chip | Off-chip (FPGA) | Off-chip (Software) | On-chip |
