Table 4 Summary of reported simulation frameworks for the study of memristive hardware neural networks
From: Hardware implementation of memristor-based artificial neural networks
Simulation Framework | Year | Platform | Training | Simulation type | Open Source | Type of ANN | Compatible dev. | Energy | Accuracy | Power | Latency | Variability | RL | CL | CMOS | GPU |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Tensorflow224 | 2015 | Python | Yes | Neural network | Yes | MLP, CNN | No dev. | No | Yes | No | No | Yes | No | No | No | Yes |
Pytorch223 | 2017 | Python | Yes | Neural network | Yes | MLP, CNN | No dev. | No | Yes | No | No | Yes | No | No | No | Yes |
NEURON285 | 2006 | Python | Yes | Neural network | Yes | SNN | No dev. | No | Yes | No | No | Yes | No | No | No | Yes |
Brian2225 | 2019 | Python | Yes | Neural network | Yes | SNN | No dev. | No | Yes | No | No | Yes | No | No | No | Yes |
NEST226 | 2007 | Python | Yes | Neural network | Yes | SNN | No dev. | No | Yes | No | No | Yes | No | No | No | Yes |
BindsNET227 | 2018 | Python | Yes | Neural network | Yes | SNN | No dev. | No | Yes | No | No | Yes | No | No | No | Yes |
Memtorch286 | 2020 | Python, C++, CUDA | No | Neurla network | Yes | CNN | RRAM | No | Yes | No | No | Yes | No | No | No | Yes |
2015 | C++ | No | Architecture | Yes | Memory | RRAM | Yes | No | Yes | Yes | No | No | No | No | No | |
PUMA154 | 2019 | C++ | No | Architecture | No | MLP, CNN | RRAM | Yes | Yes | Yes | Yes | No | No | No | Yes | Yes |
RAPIDNN247 | 2018 | C++ | No | Architecture | No | MLP, CNN | RRAM | Yes | Yes | Yes | Yes | Yes | No | No | Yes | No |
DL-RSIM228 | 2018 | Python | No | Architecture | No | MLP, CNN | RRAM | No | Yes | No | No | Yes | No | No | No | Yes |
PipeLayer246 | 2017 | C++ | Yes | Architecture | No | CNN | RRAM | Yes | Yes | Yes | No | No | No | No | No | |
Tiny but Accurate230 | 2019 | MATLAB | No | Architecture | Yes | CNN, ResNET | RRAM | Yes | Yes | Yes | No | No | No | No | No | No |
Yuan et al.231 | 2019 | C++, MATLAB | Yes | Architecture | Yes | No data | RRAM | No | Yes | Yes | No | No | No | No | No | Yes |
Sun et al.229 | 2019 | Python | Yes | Architecture | No | MLP | PCM, STT-RAM, ReRAM, SRAM, FeFET | Yes | Yes | Yes | No | Yes | No | No | No | No |
A. Chen248 | 2013 | MATLAB | No | Circuit | Yes | MLP | RRAM | No | No | Yes | No | Yes | Yes | No | No | No |
CIM-SIM242 | 2019 | SystemC (C++) | No | Architecture | Yes | SLP | RRAM | No | No | No | No | No | No | No | No | No |
2018 | Python | No | Architecture | Yes | CNN | RRAM | Yes | No | Yes | Yes | Yes | No | No | No | Yes | |
NVSIM245 | 2012 | C++ | No | Circuital | Yes | Memory | PCM, STT-RAM, ReRAM, Flash | Yes | No | Yes | Yes | No | No | No | No | No |
CrossSIM287 | 2017 | Python | No data | Circuital | Yes | No data | PCM, ReRAM, Flash | No | Yes | No | No | Yes | Yes | No | No | Yes |
NeuroSIM91 | 2022 | Python, C++ | Yes | Circuital | Yes | MLP, CNN | PCM, STT-RAM, ReRAM, SRAM, FeFET | Yes | Yes | Yes | No | Yes | No | No | No | Yes |
NVM-SPICE252 | 2012 | Not specified | No | Circuital | No | SLP | RRAM | Yes | No | Yes | Yes | Yes | No | No | Yes | No |
IBM Analog Hardware Acceleration Kit232 | 2021 | Python, C++, CUDA | Yes | Neural network | Yes | MLP, CNN, LSTM | PCM | No | Yes | No | No | Yes | No | No | No | Yes |
Fritscher et al.256 | 2019 | Mixed (VHDL, Verilog, SPICE) | No | Circuital | No | MLP | PCM, STT-RAM, ReRAM, SRAM, FeFET | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Aguirre et al.253 | 2020 | Mixed (Python, MATLAB, SPICE) | No | Circuital | No | MLP | PCM, STT-RAM, ReRAM, SRAM, FeFET | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |