Fig. 4: Optimization scalability.

a Experimental and b simulated CZXEB cycle error benchmarks (e_c, boxes) in optimized (black) and unoptimized baseline (red) configurations of variable size. Simulated processors have size and connectivity corresponding to surface code logical qubits with distance d. The crossover standard (green), outlier standard (orange), and stitched configurations (purple) are shown for comparison. The solid lines are fits of the saturation model to the optimized (black) and baseline (red) benchmark means. Some boxes have been horizontally shifted to reduce overlap. In (a), N < 40 boxes combine benchmarks from multiple configurations to boost statistics. The x axis in (b) is linear in d with N = 2d² − 1 and the shaded region illustrates the experimentally accessible regime of our processor. c Benchmark heatmaps illustrating stitching of our N = 68 processor and (d) N = 1057 simulated processor. Outliers are not substantially amplified at seams (dashed lines), which is our primary concern. The dashed regions in (d) illustrate that stitching the d = 23 logical qubit with R = 4 is equivalent to stitching four d = 11 logical qubits.