Fig. 4: Stretchable a-IGZO transistor array, logic gates, and 7-stage ring oscillator.

a Transfer characteristics of 7 × 7 stretchable a-IGZO transistor array (0%, 15%, 30%, and 50% strain). b Micrographs of 7 × 7 stretchable transistor array under 0%, and 30% strain. c Circuit diagram, output signals, drain current and voltage gain of stretchable pseudo-inverter. d Micrographs, output signals, and oscillating frequency of stretchable 7-stage ring oscillator under 0%, 15%, and 30% strain. e Micrographs of logic gates including inverter, NAND and NOR gates under 0% and 30% strain. f Input and output signals of inverter, NAND and NOR gates under 0%, 15%, 30%, 40% and 50% strain.