Fig. 2: The design details of Speck.

a The power composition of AI systems. b The case of high resting power. When the resting power is too high, the gain brought by the advanced algorithm design is hard to lower the total power effectively. c The case of low resting power. Low resting power helps unleash the power of advanced algorithm design. d Speck physical display. e Speck is a sensing-computing end-to-end SoC that integrates DVS and asynchronous neuromorphic chip. f Typical application scenarios of always-on Speck. g The fully asynchronous architecture of Speck. The DVS events come from the on-chip sensor. After an asynchronous event pre-processing core, events can be routed to SNN cores for processing. In Fig. S1, we give the layout of Speck. h The SNN core microarchitecture (more details in Fig. S5). Each SNN core can be simply considered as a spiking convolution layer with an integrated pooling layer. When a spike (event) is received at the input of the core, a fully asynchronous convolution operation is performed to calculate all required neuron updates caused by the received input spike. i Asynchronous event-driven convolution. Based on the address of the input event or spike, the address mapping function outputs the address of the neuron and synapse that need to perform synaptic operations (more details in Fig. S4).