Fig. 2: Fabricating an on-chip p-bit. | Nature Communications

Fig. 2: Fabricating an on-chip p-bit.

From: Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

Fig. 2

a 3D schematic of the proposed design for an on-chip p-bit core, using a stochastic MTJ and 2D MoS2 field-effect transistor (FET). b Side cross-section view of the MTJ stack, with the fixed- and free-layer denoted. c Top scanning electron microscopy (SEM) view of an example MTJ pillar of the same nominal dimensions as the stochastic MTJ in the interconnected on-chip device. d Optical microscope and (false-color) tilted-SEM images of an example finished MTJ device. e Cross-section schematic of the 2D MoS2 FET. f Optical microscope and SEM images of the 2D FET, showing the interdigitated contacts that are used to attain high-current drives.

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