Fig. 3: Characterization & measurement of the interconnected on-chip p-bit core.

a Minor loop of the stochastic MTJ used in the p-bit, with the 50–50 point indicated by the dashed line. b Graph showing the resistance fluctuations of the stochastic MTJ when biased at the 50–50 point. c Histogram data for the antiparallel- and parallel-state dwell times, used to extract the mean dwell time in each state. d Graph showing the device characteristics of the pristine MoS₂ FETs using the interdigitated contacts design, before being connected to the stochastic MTJs. e Graph showing the device performance of the FET used in the on-chip p-bit core. The degradation was observed after integrating the FET with the stochastic MTJ device. f Schematic of the design for the on-chip p-bit core demonstration. g Optical microscope image showing the interconnected on-chip device and the probes used for measurement. h Graph showing the operation of an on-chip p-bit core, with an output (V_{INVERTER INPUT}) that exhibits stochastic fluctuations that are tunable with the modulation of the FET gate voltage (V_IN). The observed fluctuations are obtained via repeated measurements of V_{INVERTER INPUT} at each V_IN. These fluctuations are shown in the inset figures, with time-series data of the fluctuations for V_IN = −3.8 V (red inset) and for V_IN = −2 V (green inset).