Fig. 1: Structure and device characterization of the VSFET.
From: High drain field impact ionization transistors as ideal switches
a Three-dimensional schematic of the VSFET fabricated on SOI. D, Gr, TG, S, and N + : Drain, graphene, Top-gate, Source, and N-type ion implantation area. Schematic diagram of the energy bands of the VSFET in the off-state (b) and on-state (c). EC, EV, EFS, and EFD: conduction band energy, valence band energy, source fermi level, and drain fermi level, respectively. DFT-simulated electric field contour in vertical (d) and lateral (e) direction on the VSFET. X1, X2, Z1, Z2 are line cuts in (d) and (e), respectively. f Vertical electric field of the VSFET using DFT-simulated. X1 represents the vertical electric field near the graphene-silicon heterojunction drain end, and X2 represents the vertical electric field in the silicon channel part close to the source. g Lateral electric field of the VSFET using DFT-simulated. Z1 represents the lateral electric field in the silicon region, and Z2 represents the lateral electric field in the graphene layer. h Top-view false-color SEM image of a VSFET. Scale bar, 10 µm. i Cross-sectional scanning transmission electron microscopy image of the VSFET. Corresponding EDS elemental map showing the distribution of C and Si elements. j The zoom-in image in the orange rectangle in (i). Scale bar, 2 nm. k Comparison of experimentally measured logarithmic-scale transfer characteristics of the fabricated VSFET (red curve) and MOSFET (blue curve) at VDS = 3 V.
