Fig. 4: Cryogenic characteristics of III-V-based DC and RF routing circuits monolithically integrated on Si.
From: Cryogenic III-V and Nb electronics integrated on silicon for large-scale quantum computing platforms
a Schematic of 1-to-4 DC routing circuit diagram. There are one input and four outputs with four control gates (A1, A2, B1, B2). b Resistance of Nb versus temperature (normalized to the resistance at 10 K), showing the transition temperature of 8 K. Inset includes resistance values measured up to 300 K. c Input-output waveforms under different input voltages, showing the functionality of the cryogenic routing. d Resistance benchmark for the presented routing circuits compared with conventional CMOS-based approach (22 nm FDSOI) in the case of scaled structure. The layout of the routing circuit is found in Supplementary Fig. 8. The resistance is normalized to the resistance of a CMOS-based routing circuit with 32 gates. e Schematic of 1-to-2 RF routing circuit diagram. There are two RF output ports (RF1 and RF2) with one common port (RFC). The C1 and C2 are control gates. f S21 versus frequency under different Vov of the control gate. g Output waveform under different input signal frequencies. h Output waveform for a 6 GHz input signal with path 1 off and path B on. i Static power consumption as a function of Vov measured at 4 and 300 K. The line represents the typical operation region with a Vov range of −0.1 to 0.4 V.
