Fig. 2: FeFET device basics. | Nature Communications

Fig. 2: FeFET device basics.

From: Demonstration of high-reconfigurability and low-power strong physical unclonable function empowered by FeFET cycle-to-cycle variation and charge-domain computing

Fig. 2

a FeFET structure and TEM image. b Layout of 2FeFET-1C PUF cells, each consisting of two FeFETs and one capacitor. c Micro-graph of the fabricated chip. d The proposed 2FeFET−1C PUF cell. The challenging bit is input via BL1 and BL2, generating a local result at node X, which is coupled to SL via the capacitor. e \({I}_{{{{\rm{DS}}}}}\)-\({V}_{{{{\rm{GS}}}}}\) curves of one FeFET across 100 write cycles, showing response to -5 V/2.8 V/3.6 V/4.5 V writes pulses for writing the FeFET to various \({V}_{{{{\rm{TH}}}}}\) states. The nonvolatility and ultra-high on/off ratio enable FeFETs with low-power operations. Consistent C2C variation is observed across all write pulses. f Comparison of C2C and D2D variation in FeFETs. The C2C variation extracted from 8 FeFETs over 100 cycles shows significantly less variance than the D2D variation across 63 FeFETs. Therefore, using D2D variation for registration would degrade reconfigurability. g The FeFET C2C variation is evaluated under different write pulses and device dimensions. The measured C2C variation remains stable and significant, which enhances the robustness of the proposed FeFET-based PUF.

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