Table 1 Comparison with prior works

Reference	This work	IEDM 2023³⁹	NE 2018²⁹	NC 2021²⁸	SA 2022³⁰	NE 2021³⁵	NE 2023³⁴	Roel, M.²³
Technology	FeFET	FeFET	RRAM	RRAM	RRAM	GFET	STT-MRAM	CMOS (APUF)
PUF type	Strong	Strong	Strong	Weak/ Strong	Weak	In middle^a	Weak	Strong
Computation mode	Charge domain	Current domain	Current domain	Current domain	Current domain	Analog ADC	N/A	Delay path
Uniformity	50.00%	49.5%	49.5-50%	49.02%	50.13%	~50%	Not reported	Not reported
NIST test	Passed	Passed	Passed	Passed	Passed	Not reported	Passed	Not reported
Uniqueness	49.98%	50.01%	50.0%	48.3%	50.52%	47–50%	49.99%	47.13%
BER	0.7% @85 °C	1.7% @100 °C	1.1–3% @90 °C	~0% @85 °C	~5% @100 °C	0-7% @125 °C	0%	3.04%
Reconfigurability	50.02%	Not reported	N/A	40.06%	Concealable^b	34–50%	N/A	N/A
Scalability	High	Low	Low	Low	Low	Low	High	Low
Readout energy (Basic)	1.89fJ per bit^c	3fJ per bit^d	20fJ per bit^e	51.2fJ per bit	2.404pJ per bit	<5pJ per bit	Not reported	1.1pJ per bit
Readout energy (Enhanced^f)	15.67fJ per bit^c	N/A	N/A	102fJ per bit	N/A	N/A	N/A	Not reported
Area per cell	1 μm²	~2500 μm²	~3.5 μm²	~0.01 mm²	>0.75 μm²	>0.5 μm^2g	Not reported	0.213 mm²
ML attack accuracy	52.1%	~50%	55%	54%	N/A	52.5%	N/A	100%

^aThe PUF cannot generate an exponentially large number of CRPs as strong PUFs but is able to generate more CRPs than weak PUFs.
^bConcealable PUF means that the PUF can hide the stored data (i.e., the generated CRPs) when attacked and recover them afterward. Note that the CRP space before and after hiding is the same without reconfiguration.
^cFeFET-based PUF array, SA, and XOR gates are included in the evaluation.
^dHSPICE simulation result.
^eThe energy of the peripherals is not considered.
^fSome PUFs are enhanced using XOR or recurrent structure to obtain the listed ML attack resilience.
^gThe data include the channel area of GFETs only.

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