Fig. 4: Sensing, memory, and preprocessing of the MIR synaptic device array.

a Optical image of a 4 × 4 MIR synaptic transistor array. b Synaptic transistor array integrated with a 16-channel real-time readout circuit. c Schematic of the MIR laser light moving upon the device array following a flipped “L” trajectory. d Relationship between image pixels and optical input through array preprocessing. e Vout measured from the readout circuit at pixels involved in the trajectory in the device array. f Normalized current mappings during MIR laser movement (first 10 s) and memory fading (after 10 s). Source data are provided as a Source Data file.