Fig. 5: Fabrication of logic gates. | Nature Communications

Fig. 5: Fabrication of logic gates.

From: Revisiting the role of oxidation in stable and high-performance lead-free perovskite-IGZO junction field-effect transistors

Fig. 5

a OM image and corresponding circuit diagram of a logic circuit for the NOT gate (scale bar = 500 μm). b Voltage-transfer and c gain characteristics of the NOT gate under various VDD. d, e OM images and corresponding circuit diagrams of logic gates for the NAND and NOR gates at VDD = 1 V (scale bar = 500 μm). f Four possible logic combinations (0,0), (1,0), (0,1), and (1,1) with the corresponding output voltages of the NAND and NOR gates.

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