Fig. 1: Wafer-scale carbon nanotube charge-trapping transistors.

a Carbon nanotube charge-chapping transistors on a 4-inch wafer, with b–d showing the device configuration, zoomed-in device array, and scanning electron microscopic carbon nanotube thin-film. Scale bars –2 cm, 100 μm, 1 mm, and 1 μm. e Transfer outputs of 300 randomly sampled transistors, showing consistent yet varying non-volatile memory switching. f Reconfigurable memory, showing over 32 easily distinguishable stable states. Possibility mass function (PMF) of g the memory window, h the mobility extracted from the transfer outputs, and i the sub-subthreshold swing, sampled from 300 random transistors across the wafer. j Cycling high/low conductance state configuration with 1 kHz pulsed gate signal, showing stable state configuration across 1000 cycles. k Cycling challenge-responses as probed by positive and negative 1 MHz pulsed drain signals at a medium conductance state, showing stable yet varying responses over 10⁶ cycles. The 10⁶ raw data points are plotted with 1000-point intervals due to the limitations of the plot drawing software.