Fig. 2: Chip-scale PUFs and operation.

a Operation diagram of the PUFs. In the prototyped chip, 40 PUFs are fabricated, where each PUF consists of nine carbon nanotube transistors connected via a common drain. In operation, gate pulses are applied to configure the individual transistors, a 1 MHz pulsed voltage signal is applied to the drain as the challenge, and the sources output current pulses as the response that are then converted and binarized to generate the digitized PUF primitives. In binarization, each of the response pulses generates 12 binary digits via ADC. PUF primitives of a 108-bit length are generated. See Supplementary Fig. 4 for the optical microscopic images of the PUF chip, and Supplementary Fig. 6 for the hardware operation of the PUFs. b Configuration and resetting of the first PUF, denoted as PUF₁, from the initial state, with c zoom-in plots showing the first three consecutive states. The initial state means all the individual transistors are configured to the initial high conductance states. d Configuration and resetting of PUF₁ from a random state, s. e Bit error rate (BER) of our PUFs at the initial, final, and three other states. See also Supplementary Fig. 8 for the detailed BER assessment. All the BER is lower than 1%, proving the operational reliability of our PUFs.