Fig. 1: Stabilizer measurements on a five-transmon device.
From: Real-time processing of stabilizer measurements in a bit-flip code
a Schematics of the device implementing the bit-flip code with the data qubits D1, D2, D3 and the ancilla qubits At, Ab. Triangles represent the bus resonators coupling the qubits at their vertices. A Josephson Parametric Amplifier52 (Converter53) enhances the readout of At (Ab). b Gate and measurement sequence for one round of stabilizer measurements. CNOT gates map the parity of D1–D2 (D2–D3) onto At (Ab) and are applied concurrently two at a time. c Simplified setup diagram highlighting the closed loop central to active error correction and decoding. For QEC cycles n ≤ N, the processor stores the stabilizer results \({\{{a}_{{\rm{t}}},{a}_{{\rm{b}}}\}}_{n}\) acquired by the receivers. When n = N, it executes a custom function (here decoder) and broadcasts the result back to the pulse sequencers for conditional gates (here \(\hat{X}\)). The same framework is used to execute a logical data measurement, where the majority function is applied on a single acquisition {d1, d2, d3}.
