Extended Data Fig. 3: The electrical properties of a typical 3-layered stacked Bi2O2Se/Bi2SeO5 GAAFET.
From: Low-power 2D gate-all-around logics via epitaxial monolithic 3D integration
a, b, Structural schematics (a) and optical image (b) of as-fabricated 3-layered stacked Bi2O2Se/Bi2SeO5 GAAFET. c–e, output (c) and transfer (d, e) characteristics of the as-fabricated 3-layered stacked Bi2O2Se/Bi2SeO5 GAAFET. f, g, The repeated measurement of the 3-layerd stacked GAAFET shown in (b) with 50 cycles dual-direction sweep. Inset: the hysteresis detail of the 2D GAAFET for 50 cycles dual-direction sweep. h, The absolute values (left axis, top), the relative fluctuation (right axis,top) of the subthreshold swings (SS) and the off-state, on-current in 50 cycles dual-direction sweep. The thermionic limit of SS was included by dashed line.
