Fig. 3: Electronic properties of ferroelectric domains in MoS₂.

a, Two-pass PM-KPFM map of the surface potential acquired with V_a.c. = 5.75 V, and a time-average probe-sample distance of 37 nm during the second pass. The blue boxed inset magnifies the area used to extract numerical values of 2ΔV. The lower left inset shows the schematic of PM-KPFM measurement set-up. Scale bars 0.5 μm (upper) and 2 μm (lower). b, Typical histogram analysis used to extract surface potential difference. In this case, the data from the blue boxed area in a were used; for details and analysis of other areas see Supplementary Information. a.u., arbitrary units. c, Calculated surface potential distribution for experimentally relevant domain sizes. Inset shows the potential drop across the domain walls calculated considering (narrow line) and ignoring (bold line) piezoelectric charges. Scale bar, 50 nm. d,e, PM-KPFM surface potential map of a sample with no gate voltage (d) and with back-gate voltage applied indicating disappearance of the potential variation when free electrons are introduced (e). Scale bars, 1 μm. f,g, Hysteretic behaviour of electrical conductivity G_sd of our artificially made ferroelectric semiconductors as a function of top-gate electric field (E_t) for different back-gate electric fields (E_b). The shown curves are for 1L MoS₂ on top of 1L MoS₂ at 350 K (f) and 3L/3L MoS₂ at room temperature (g) twisted by 0° to achieve the 3R interface. We used the top gate for recording hysteresis because it covers only the twisted region whereas the bottom gate influences a much larger area, including contact regions. h, Similar measurements on a reference 2L/2L sample twisted by 0°, which produces a 2H interface and displays much smaller hysteresis with the opposite sign (room temperature).