Extended Data Fig. 10: SPICE modelling of CMOS variability.
From: Equivalent-accuracy accelerated neural-network training using analogue memory
a–f, Monte Carlo circuit simulations of parameter variability in 3T1C cells: measured conductance versus instantaneous voltage on the capacitor VC (a); PDF of the measured conductance at VC = 0.5 V (b); change in voltage versus the instantaneous voltage for up pulses (c); PDF of change in up voltage at VC = 0.5 V (d); change in voltage versus the instantaneous voltage for down pulses (e); and PDF of change in down voltage at VC = 0.5 V (f). Each graph shows data from 1,000 trials. Bold lines in a, c and e and dotted lines in b, d and f show the nominal transistor response. a, b, Variability in the read transistor whose gate is tied to the capacitor; c–f, variability due to variation in threshold voltage in the PMOS pull-up/NMOS pull-down FETs.
