Extended Data Fig. 5: 2-bit multiplier digital states.
(a) Logic diagram of the 2-bit multiplier with its corresponding (b) truth table. (c) A schematic (left) and experimental image (right) of the material and conductive network for the 2-bit multiplier operation as determined from the design process. (d) A schematic (left) and experimental image (right) of the 16 possible configuration states with the binary inputs (A1 B1 A2 B2)2 shown in green and output (QP4 QP3 QP2 QP1)2 in red. Connected networks for each output are bolded and highlighted in green or yellow.
