Fig. 1: Vertical scaling versus in-plane scaling of semiconducting circuits.
From: Van der Waals polarity-engineered 3D integration of 2D complementary logic

a, Schematic illustration of the routes of scaling in Si and vdW technologies. b, Molecular structure of a pristine MoS2 layer. The difference in charge density distributions of slight electron doping with respect to a neutral layer for an isosurface of 10 μe Bohr−3 above the Fermi level is superimposed on its molecular model. c, Schematic diagram of the n-type MoS2 in the conventional pristine state, with the Fermi level (red solid line) positioned in the vicinity of the conduction band minimum (CBM) in MoS2. d, Same plot of differential charge density distributions as b, but in a MoS2–CrOCl heterostructure. In b and d, the charge carrier types of electrons and holes are marked in pink and green, respectively. The atom-symbols used in b and d are illustrated in the bottom part of b. Clear n-type behaviour on electron doping can be seen in b, while in the MoS2–CrOCl heterostructure case in d, most of the doped electrons are transferred to the CrOCl side. e, Schematic band alignment diagram of the MoS2–CrOCl heterostructure under finite vertical negative electric field (corresponding to the negative bottom gate voltage in our experimental configurations), indicating the realization of a p-type semiconducting MoS2 with the Fermi level (red solid line) positioned in the vicinity of the valence band maximum (VBM) in MoS2.