Extended Data Fig. 7: Field effect curves of each transistor in the vertical 4T-SRAM.
From: Van der Waals polarity-engineered 3D integration of 2D complementary logic
For a typical vertical 4T-SRAM device as shown in Fig. 4j in the main text (or in Extended Data Fig. 6d), we characterized each transistors that are inter-connected for the test of SRAM. The labels (i.e., TNi, i = 1, 2; and TPj, j = 1, 2) of each transistor follows the convention indicated in Extended Data Fig. 6b. Field effect curves of them are shown respectively: (a) the bottom MoS2 n-FET TN1, (b) the bottom CrOCl/MoS2 p-FET TP1, (c) the top MoS2 n-FET TN2, and (d) the top CrOCl/MoS2 p-FET TP2. All data obtained at room temperature with a source-drain voltage Vds = 0.1 V.
