Fig. 2: Electrical performance of MoS₂–CrOCl complementary FETs.

a,b, Source–drain current I_ds as a function of back gate voltage V_bg, measured for a typical MoS₂–CrOCl FET (a) (orange line) and a conventional pristine MoS₂ FET placed on h-BN (b) (blue line). Trace and retrace (as indicated by the solid black arrows) are recorded in a and b, exhibiting negligible gate hysteresis. Measurements in a and b are carried at V_ds = 0.1 V and at room temperature. The inset in a shows an optical micrograph of MoS₂ FETs made from the same MoS₂ flake, but with different polarities when placed on CrOCl or h-BN. Each constituent layer is highlighted by coloured dashed lines. The inset in b shows the same data as in a and b, but plotted on a log scale. c, False-coloured SEM image of a vertically stacked MoS₂ complementary logic inverter. d, Output voltage V_out as a function of input voltage V_in at various supply voltages V_DD. e, The gain for each of the curves in d. f, Performance of state-of-the-art p-type MoS₂ FETs in the parameter space of on/off ratio and hole mobility at room temperature. Data points of this work (solid red squares) are discussed in more detail in Supplementary Fig. 15. In f, the error bar for the on/off ratio is defined as 1/δI_off, with δI_off being the standard deviation of I_off in each device, while maximum I_on is fixed. The error bar for the hole mobility is defined as the standard deviation of the γ × dI_ds/dV_g at the vicinity of the maximum, where γ is a coefficient obtained from the sample, written as \(\frac{L}{WC{V}_{{\rm{ds}}}}\). L, W, C and V_ds are respectively the length, width, the gate capacitance and the source–drain voltage for the measured device. Scale bars, 10 μm (a,c).