Fig. 4: Towards future 3D integration of 2D semiconducting complementary logic.
From: Van der Waals polarity-engineered 3D integration of 2D complementary logic
a, Logic operation of Vin–Vout characteristics of a typical 3D-NAND device with 14 vertically integrated vdW layers as shown in Fig. 3c. A VDD of 3 V, GND of −3 V and Vin = ±3 V for inputs A and B were applied during measurements. b, Dynamic NAND performance of the same sample as in a tested at a pulse period of 400 ms. c,d, show the input waveforms (c) and output level (d) of a typical 3D-SRAM device with 14 vertically integrated vdW layers. e, Field-effect curves of p-type MoSe2 (red curves, with the statistics of 12 devices) and p-type MoS2 (green curves, with the statistics of 8 devices) induced by coupling of the CrOCl substrates. Vds = 0.1 V is used in the measurements. f, Output performance of a typical p-type MoSe2–CrOCl transistor, with a maximum Ids reaching 0.3 mA at Vds = 2 V. The channel length and width of the tested device are 3 μm and 5 μm, respectively. g, Logarithmic plot of transfer curves of typical p-type MoSe2–CrOCl transistors, measured using the transfer length method (TLM). A Vds of 0.1 V was used in the measurement. h–j, False-colour SEM images of typical 4T-SRAM devices based on the planar-FET (h), CFET (i) and VIP-FET (j) architectures, with distinctive colour-coding for their VDD, GND, Vin and Vout electrodes in green, purple, yellow and blue, respectively. k–m, art illustrations of the devices pictured in h (k), i (l) and j (m). Devices in i–j are plasma-etch patterned into square areas for visual clarity. n, An outlook of future 3D integration of 2D VIP-FETs, based on the technology described in this work. Scale bars, 10 µm (h–j).
