Extended Data Fig. 1: VdW polarity-engineering of MoS₂ on CrOCl.

(a) Schematic drawing of the vdW polarity-engineering in a vertical 2D heterostructure. Here the structure is illustrated into two parts: left, MoS₂ semiconducting channel is placed on a few-layered CrOCl that is intercalated between MoS₂ and the supporting h-BN; and right, MoS₂ semiconducting channel is in contact directly with the top surface of h-BN. The drawing corresponds to the scenario of a typical experimental device as shown in the inset of Fig. 1a in the main text. The left part scenario will be further discussed here. (b) Optical micrograph of a typical MoS₂/CrOCl device with a pristine surface of CrOCl (i.e., freshly exfoliated and without O-plasma treatment). (c) Field effect curve of the CrOCl-supported MoS₂ device, measured at V_ds = 0.1 V at room temperature. The device exhibits a typical p-type behavior, with negligible hysteresis (trace and re-trace are recorded as indicated by the black solid arrows). In this case, the vdW polarity-engineering works perfectly as the conventional n-type behavior of a MoS₂-FET is switched into p-type by simply a touch of few-layered vdW insulator (due to strong interfacial couplings). It is noteworthy that, as shown in (d), when the surface of CrOCl flake is treated by a mild O-plasma (50 Watt, 180 sccm flow rate of oxygen, with an Aluminum etching tunnel in a Yamato-PR 500 plasma reactor) for 30 s before stacking MoS₂ on top of it, the transfer curve of the resulted device is then very hysteric and is of n-type (instead of p-type), even the macro-scale structures look the same for both devices in (b) and (d). It thus speaks highly the importance of a clean/pristine interface, which plays a key role in the vdW polarity-engineering process. Scale bar in (b) and (d) are 10 μm.