Extended Data Fig. 2: Six-vdW-layer vertically assembled inverter.
From: Van der Waals polarity-engineered 3D integration of 2D complementary logic
(a) Art view of the MoS2-CFET inverter using the vdW interfacial doping scheme described in this work. The CFET consists of 2 FETs with n- and p-type polarity for the MoS2 channel without (the bottom one) and with (the top one) CrOCl intercalation, respectively. (b) Illustration of the fabrication process of the n-type MoS2-FET part of the CFET: 1) A flake of few-layered MoS2 was exfoliated onto a SiO2/Si substrate; 2) Metal electrodes served as source and drain were deposited by standard e-beam lithography followed by evaporation of Cr (5 nm)/Au (30 nm); 3) A spacing/dielectric layer of few-layered h-BN was transferred on top of the MoS2 channel by a polypropylene carbonate stamp; 4) Top-gate electrode was evaporated. (c) Illustration of the fabrication process of the p-type MoS2-FET part of the CFET: 5) Following step 4, another spacing/dielectric layer of few-layered h-BN was transferred by a polypropylene carbonate (PPC) stamp; 6-7) few-layered MoS2 interfaced with few-layered CrOCl as a p-channel were transferred by a polydimethylsiloxane (PDMS) stamp; 8) Metal electrodes were evaporated to form the source and drain in the top semiconducting channel. (d) The schematic diagram of the CFET inverter.
