Extended Data Fig. 3: Power consumption of a typical MoS2 CFET inverter.
From: Van der Waals polarity-engineered 3D integration of 2D complementary logic
(a) Optical micrograph image of a typical tested CFET device (sample #S1b), constructed with the same structure as the illustration in Extended Data Fig. 2a. Scale bar is 10 μm. (b) Voltage transfer characteristics of the CFET inverter in (a) at different VDD. The corresponding voltage gains for each voltage transfer curve are shown in the inset in (b) using the same color code. (c) Power consumption (defined as VDD × IDD) of the CFET are shown as a function of Vin for different VDD. For example, the peak power consumption is found to be ~ 518 pW for VDD = 1 V. Same color codes for the data are used in (b) and (c).
