Extended Data Fig. 5: VIP-FET based 3D NAND logic made of over-10-layer vdW heterostructure.

(a) The schematic diagram of the conventional planar 4-transistor (4T) NAND logic circuit (whose 3D inter-connected version is illustrated in Fig. 3b-c in the main text). The 2 n-type and 2 p-type transistors are labelled as T_N and T_P, respectively. It is seen that in a conventional planar scheme, the NAND logic takes up 4 unit areas, while the stacked-up version by 3D integration will shrink the total effective channels into 1 single unit area. The vdW polarity-enginnered VIP-FET thus is particularly suitable for this vertical integration approach. As shown in (b), the cartoon illustration of the detailed vdW layers with a vertical stacking sequence (14 vdW layers in total, with 2 p-FETs and 2 n-FETs) is given, in order to achieve the same function as the planar NAND in (a) but rather fabricated in a 3D manner. Such 3D NAND structure with 14 vdW layers is further realized by interconnecting the inter-layer electrodes according to the architecture illustrated in Fig. 3c in the main text. Notice that T_N and T_P in the vertical 3D NAND in (b) are realized by MoS₂ and MoS₂/CrOCl, respectively.