Extended Data Fig. 6: Timing diagram of erasing and reading operations.
From: A full-featured 2D flash chip enabled by system integration
a, Full-chip erasing operation. The host computer sends the commands 06H and C7H. The all_en (to select all WLs) signal is activated, selecting the entire chip. The logic module generates an erase enable signal for the analogue circuit, while simultaneously producing a synchronised clock signal to apply the corresponding voltages to all cells. b, 32-bit parallel reading operation. The host computer sends the command 03H. In this timing diagram, address “00H” (corresponding to WL[0]) is selected for reading. The read enable signal is activated, and all the 32 BLs are applied with a reading bias. When the rd_clk (read clock) signal is activated, the sense amplifier amplifies the readout data, then sends the 32-bit data to the logic module, where the data is processed from parallel to serial. When the o_so_en (data output enable) signal is activated, the logic module transmits the data o_padout (data output) to the I/O module for data readout.
