Fig. 2: The full-stack on-chip process.
From: A full-featured 2D flash chip enabled by system integration
a, The 3D architecture of the fabricated 2D flash chip. Left, the CMOS die serves as the substrate, with a PA layer of 800 nm for isolation and TGVs for communication. Right, modular design for converting compatibility issues to the 2D-CMOS module interface design. b, Magnified optical micrograph of the CMOS die highlighting dense random circuit routing. Inset, corresponding atomic force microscopy (AFM) image with roughness RMS of 1.35 nm (amplitude range of 5 nm). c, AFM image of the 2D flash integrated on the CMOS die (amplitude range of 8 nm). The conformal adhesion of 2D materials to the rough CMOS die surface facilitates stress relief. d, Statistical results of memory window characterization of the 2D flash. The 2D flash cells fabricated by the conformal adhesion on-chip process exhibit compact, distinguishable Vth distributions for on–off states (red solid line, 60 cells extracted from Extended Data Fig. 1a). The non-ideal behaviour, caused by yield and uniformity limitations, exhibits a broader distribution with overlap (blue dashed line). e, Schematic of the comprehensive protection in the 2D-friendly packaging. Left, region-specific ESD protection. ESD1 for WL/BL/SL, ESD2 for power/ground, ESD3 for inputs and ESD4 for outputs. The hatched areas denote the internal circuit associated with the corresponding pads. Top right, comparison of 2D specialized ultrasonic wire bonding with low thermal and strain budget (right) to conventional thermocompression approach with high thermal and strain budget (left). Bottom right, room temperature (RT) curing in a die attachment process. Scale bar, 5 μm (b,c). VDD, high power supply voltage; VSS, low power supply voltage.
