Extended Data Fig. 1: The performance of 2D flash cells fabricated through full-stack on-chip process.
From: A full-featured 2D flash chip enabled by system integration
a, b, Lossless and high uniformity of 2D flash cells. Dual sweep transfer characteristic curves of 2D flash cells fabricated on highly flat SiO2 substrate (60 cells) and on CMOS substrate (60 cells) through full-stack on-chip process (a). The ON/OFF current extracted from (a) at VGS = 0 V (b). c, d, Typical transfer characteristic curves among 1,008 cells (c) and output characteristic curves among 1,012 cells (d) of state-ON and state-OFF. The 2D flash cells are programmed by progressive amplitude pulses, with a fixed pulse width of 20 ns. e, f, TCAD simulation for programming energy consumption evaluation. The device structure for simulation (e). The channel length (2 μm) and width (2 μm) of the simulated MoS2 flash memory were the same as the fabricated 2D flash cell. The tunnelling current is simulated to be 2.3 μA under designed operation voltage and tunnelling layer thickness (f). Therefore, the programming energy consumption is evaluated to be 20 ns × 2.3 μA × 14 V = 0.644 pJ/bit. More details about the TCAD simulation method and energy consumption evaluation are discussed in Supplementary Information Section 5.
