Extended Data Fig. 3: The crosstalk suppression 2D NOR flash circuit design.
From: A full-featured 2D flash chip enabled by system integration
a, Circuit diagram of the 2D NOR flash (2 × 2 array depicted for clarity). The upper left cell is the selected cell to be programmed (red block), and the two cells adjacent to it are the half-selected cells where crosstalk may occur (blue block). The half-selected cells only exposed to 1/2 VPP. b, Simplified band diagram of selected cell and half-selected cells. The tunnelling efficiency of the half-selected cell is considerably reduced due to the lower electric field, since the tunnelling efficiency exhibits an exponential dependence on the applied voltage. c, d, The crosstalk evaluation by applying a crosstalk pulse to 100 2D flash cells (c) and consecutively applying multiple crosstalk pulses to one 2D flash cell (d). Pulse of 7 V and −7 V for programming crosstalk and erasing crosstalk, respectively. The pulse width is 100 ns.
