Extended Data Fig. 4: Circuit schematic of SA module without 2D-compatible design (SA1) (a) and corresponding reading simulation results (b).
From: A full-featured 2D flash chip enabled by system integration
In the reading operation, MP9 is first opened to pre-charge VCOMP to 5 V (VDD). The reference current IREF (typically 10%–30% of the extracted cell ON-state current) is generated using AMP1 and the external resistor, transferred to VCOMP node through the current mirror and compared with BL current IBL to generate the output signal VOUT. During pre-charge, VBL is coupled to over 3.11 V, which leads to AMP2 at the wrong working condition. Due to the relatively small 2D current (~100 nA) and large BL parasitic capacitance (CBL), it takes a long time for VBL to discharge to below 3 V through BL for AMP2 to work, resulting in read error within the target read timing.
