Figure 6
From: Reversibility and energy dissipation in adiabatic superconductor logic
Schematic of the 1-bit-erasure gate, which is composed of six AQFP gates. The input data, a and c, are copied to the output data, x and z. The output data, y, takes the majority vote of the input data, a, b, c. Therefore, the input data, b, is erased, i.e., the 1-bit-erasure gate is logically irreversible.
