Table 1 A comparison of various reconfigurable electro-optic directed logic circuits.
Structure | Extra MUX/DEMUX | Number of Operands | MRRs required in reconfigurable two-operand operation | Modulation scheme | Operation speed |
---|---|---|---|---|---|
2 × 2 Switches arraya | YES | 4 | 7 | Forward biased PIN junction | ~500 Mb/s |
2 × 2 Switches arrayb | YES | 4 | 7 | Reverse biased PN junction | 3 Gb/s |
1 × 4 Switches arrayc | NO | 4 | 2 | Micro-heater | 10 Kb/s |
1 × 3 Switches arrayd | NO | 3 | 2 | Forward biased PIN junction | 100 Mb/s |