Figure 3
From: Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET
(a) Device schematic with biased terminals, (b) Input biasing scheme (VSG(t),VDG(t)) with expected output (ID(t)), (c-i) Equilibrium band diagram. (ii) Electron hole pair generation due to impact ionization (“integrate”) increases holes in well, (iii) Barrier lowering due to stored holes in the potential well. Also, the holes start to escape through the source junction (“leak”), (iv) Once threshold is reached (“fire”), removal of VDG makes the holes escape through both the junctions bringing the barrier to its original position (“reset”). Thus, the charge dynamics enables the Leaky Integrate and Fire neuron in a PD-SOI n-MOSFET.
