Figure 1
From: Scalable excitatory synaptic circuit design using floating gate based leaky integrators
Proposed synaptic circuit. Leaky integration is realized on the FG of M2 and M11, which is incorporated into the state variable generators (a) and (b) for post and presynaptic variable, respectively. Sampling subcircuits (c) and (d) read out the current post and presynaptic variable, respectively, and relay them to (e) the storage subcircuit. This storage subcircuit converts V m to synaptic weight that is parameterized by V w.
