Figure 4
From: Scalable excitatory synaptic circuit design using floating gate based leaky integrators
Simulated weight-depending STDP behavior of the proposed synaptic circuit. (a) Dependence of ΔV w on V w when the synaptic circuit is subject to a single pair of pre and postsynaptic spikes with Δt = ±1 ms. In the gray region, ΔV w is mostly governed by the detailed balance of charge transfer via the FG in the storage element, whereas out of the gray region the VTC of M9 + M10 mainly determines the weight dependence. (b) Schematic of bidirectionally wired neurons (N 1 and N 2) that fire correlated spikes with 1 ms Δt every 50 ms. (c) Consequent synaptic bifurcation.
