Table 1 Summary of previous STDP circuit designs.
From: Scalable excitatory synaptic circuit design using floating gate based leaky integrators
Reference | Weight | State variable implementation | Weight storage element | Technology |
|---|---|---|---|---|
S. A. Bamford et al.17 | Analog | Capacitor-based leaky integrator | Capacitor | 0.35 um |
G. Indiveri et al.26 | Analog-bistable | Capacitor-based leaky integrator | Capacitor | 0.80 um |
J. V. Arthur and K. Boahen (2006)25 | Binary | Capacitor-based leaky integrator | SRAM | 0.25 um |
S. Ramakrishnan et al.27 | Analog | Current-starved inverter | FG transistor | 0.35 um |
A. Bofill-i-Petit et al.19 | Analog | OTA-based leaky integrator | Capacitor | 0.60 um |
J. M. Cruz-Albrecht28 | Analog | OTA-based leaky integrator | Capacitor | 90 nm |
R. J. Vogelstein et al. (2002)32 | Quasi-analog (discretized) | Programmed into the microcontroller | RAM | — |
This work | Analog | FG-based leaky integrator | FG transistor | 65 nm (simulation) |
