Figure 1

Structure of gate-all-around silicon nanowire transistors. (a) Schematic of the p-type gate-all-around silicon nanowire transistor. A silicon nanowire is suspended from the substrate by wet etching after silicon fin patterning. (b) Top view SEM image of the p-type silicon nanowire. The diameter of the nanowire and the gate length are directly defined by electron beam lithography. The diameter and the gate length of the silicon nanowire transistor are 20 nm and 160 nm, respectively.