Table 2 The maximum voltage gain values of the NOT logic circuit for VDD from 1 to 5V.

From: Mechanism of carrier controllability with metal capping layer on amorphous oxide SiZnSnO semiconductor

VDD E-mode TFT

1 V

2 V

3 V

4 V

5 V

Ti/Al capped-TFT

0.48

1.71

4.14

8.79

12.83

ITO capped-TFT

0.28

0.87

1.93

3.60

6.51

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