Figure 1
Detailed process flow diagrams showing the fabrication of double QDs embedded within SiO2/Si3N4 matrices via the thermal oxidation of nano-patterned SiGe spacer layers encapsulating Si3N4 layers that are deposited over ridges of poly-Si. (a) Lithographically-patterned, 20–75 nm-wide poly-Si ridges are formed over buffer layers of SiO2 on top of Si substrate. (b) Next, sequential deposition of 25 nm-thick Si3N4 and 30 nm-thick poly-Si0.85Ge0.15 layers conformally encapsulating the poly-Si ridges. Inset is the corresponding cross-sectional SEM micrograph. (c) Symmetrical spacer stripes of poly-Si0.85Ge0.15 are subsequently fabricated at each sidewall of the Si3N4/poly-Si ridges by a direct etch back process using SF6/C4F8 plasma. The widths and heights of the poly-Si0.85Ge0.15 spacer stripes are directly determined by the process times for deposition and etch back of poly-Si0.85Ge0.15 spacer layers. (d) Lithographically-patterning processes across the spacer stripes of poly-Si0.85Ge0.15 are conducted to define the lengths of the poly-SiGe spacer islands. Inset is the corresponding top-view SEM micrograph. (e) Symmetrical poly-Si0.85Ge0.15 spacer islands with widths (W)/heights (H)/lengths (L) of 20–30 nm/25–35 nm/30–40 nm are formed. Inset is the corresponding plan-view SEM micrograph. (f) Next, a pair of spherical Ge QDs is formed at each sidewall corner of the nano-patterned Si3N4/poly-Si ridge by thermal oxidation at 900 °C. (g) Finally, after a direct etch-back process in order to expose the Si surrounding the DQDs, self-aligned silicide (Salicide) external electrodes are fabricated by the deposition of either Ni or Ti, thermal annealing, and selective etching.
