Table 1 Salient Features of different LIM techniques proposed in literature.

¹⁰

BRS^a and CRS^b cells

Non-Stateful^c V-R logic (sequential logic)

14 out of 16 Boolean function realized in maximum 3 cycles, retains logic output, destructive read operation

¹¹

1 BRS

Non-Stateful V-R logic (sequential logic)

all 16 Boolean function realized in maximum 3 cycles, retains logic output, needs rectifying behavior

¹²

1 CRS

Non-Stateful V-R logic (sequential logic)

all 16 Boolean function realized in maximum 3 cycles, retains logic output, needs rectifying behavior

¹³

2 BRS (connected anti-serially)

Non-Stateful V-R logic (sequential logic)

all 16 Boolean function realized in max. 3 cycles, retains logic output

¹⁴

3 BRS

Stateful^d R-R Logic

5 basic Boolean functions can be realized in 2 cycles, retains input variables and logic output

¹⁵

1T-1R

Non-Stateful V-R logic (sequential logic)

all 16 Boolean function realized in 2 cycles (+1 read cycle), retains input variables and logic output

¹⁶

3 BRS + passive resistor

Stateful R-R Logic

NAND, AND and other logics can be realized using different number of BRS devices or cascading, retains both input variables and logic output

¹⁷

3 BRS + passive resistor

Stateful R-R Logic

Boolean function except XOR and XNOR in 1 cycle, retains input variables and output

¹⁸

1R (4 resistance states) + passive resistor

Stateful R-R Logic

all 16 Boolean operations are realized, retains logic output

This Work

2T-1R or 1T-1R (R:4 resistance states)

Non-Stateful V-R logic

5 basic Boolean functions in 1 cycle, retains initial Memory state and logic output (not storing input variables)