Table 5 SLIM bitcell count, Normalized Energy/Operation and Normalized latency count for different operations using SLIM NAND/NOR logic gate.

From: SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices

Logic Operation Type

1T-1R (NAND)

2T-1R (NOR)

#SLIM bitcells

Norm. Energy/Op

Norm. Latency

#SLIM bitcells

Norm. Energy/Op

Norm. Latency

OR

3

2×

2×

2

1×

2×

AND

2

1×

2×

3

2×

2×

NOR

4

3×

3×

1

1×

1×

NAND

1

1×

1×

4

3×

3×

XOR

4

2×

3×

5

4×

3×

XNOR

5

3×

3×

4

3×

3×

-bit Half Adder

5

2×

3×

5

4×

4×

-bit Full Adder

9

3×

6×

9

6×

6×

  1. (All values normalized w.r.t. SLIM 1T-1R NAND and provide worst-case estimates i.e. maximum device switching).
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