Figure 7 | Scientific Reports

Figure 7

From: Noise and charge discreteness as ultimate limit for the THz operation of ultra-small electronic devices

Figure 7

Schematic representation of a double-gate graphene transistor in the BITLLES simulator. The channel (in this case graphene) is sandwiched between two dielectrics. The active region of the dual-gate 2D Fet is \(\Omega =L \times (H'+H+H') \times W\), being L the gate length, \(H'\) the height of the dielectrics, H the height of the channel and W and the width of the transistor.

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