Table 2 Tolerable variation for CIFAR-10 (VGG-9 @ 88% acc.) with and without fine-tuning (FT).

From: Device quantization policy in variation-aware in-memory computing design

Dynamic range

Weight precision

Weight implemented scheme

Tolerable STD w/o FT

Tolerable STD w/ FT

GH/GL = 2

1-bit

S-MLC

0.05

0.07

2-bit

S-MLC

0.08

0.11

D-MLC

0.11

0.15

A-MLC

0.14

0.19

3-bit

S-MLC

0.08

0.11

D-MLC

0.12

0.27

A-MLC

0.2

0.28

GH/GL = 100

1-bit

S-MLC

0.1

0.17

2-bit

S-MLC

0.2

0.29

D-MLC

0.24

0.37

A-MLC

0.26

0.46

3-bit

S-MLC

0.22

0.3

D-MLC

0.27

0.66

A-MLC

0.33

0.66