Table 3 Tolerable variation for Tiny ImageNet (VGG-16 @ 48% acc.) with and without fine-tuning (FT).

From: Device quantization policy in variation-aware in-memory computing design

Dynamic range

Weight Precision

Weight implemented scheme

Tolerable STD w/o FT

Tolerable STD w/ FT

GH/GL = 2

1-bit

S-MLC

0.03

0.08

2-bit

S-MLC

0.05

0.1

D-MLC

0.06

0.12

A-MLC

0.08

0.16

3-bit

S-MLC

0.05

0.1

D-MLC

0.08

0.16

A-MLC

0.13

0.27

GH/GL = 100

1-bit

S-MLC

0.08

0.27

2-bit

S-MLC

0.13

0.24

D-MLC

0.14

0.27

A-MLC

0.18

0.39

3-bit

S-MLC

0.13

0.25

D-MLC

0.17

0.37

A-MLC

0.22

0.61