Figure 6 | Scientific Reports

Figure 6

From: Flexible, high mobility short-channel organic thin film transistors and logic circuits based on 4H–21DNTT

Figure 6

Inverter circuit design and characteristics (a) Circuit schematic of zero-VGS-load p-type pseudo-CMOS inverter. (b) Photograph of fabricated inverter circuit. (c) Measured output voltage (VOUT) and small-signal gain as a function of input voltage (VIN) for supply voltages (VDD) between − 5 and − 20 V. (d) Dynamic response of zero-VGS-load p-type pseudo-CMOS inverter with input signal frequency of 5 kHz.

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